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Usage Notes and Known Design Exceptions to Functional Specifications

4.2 Known Design Exceptions to Functional Specifications

Table 4. Table of Contents for Advisories

Title ...................................................................................................................................... Page

Advisory —Analog Subsystem: Analog Subsystem Function InitAnalogSystemClock() is Incomplete ..................... 13

Advisory —Analog Subsystem: Potential Race Condition after Executing Analog Subsystem Functions

AnalogClockEnable() or AnalogClockDisable() ............................................................................ 14

Advisory —ADC: Initial Conversion .................................................................................................. 15

Advisory —ADC: ADC Result Conversion When Sampling Ends on 14th Cycle of Previous Conversion, ACQPS = 6

or 7............................................................................................................................... 15

Advisory —ADC: Offset Self-Recalibration Requirement ........................................................................ 16

Advisory —UART: RTRIS Bit in the UARTRIS Register is Only Set When the Interrupt is Enabled ....................... 17

Advisory —VREG: VREG 'Warn Lo/High' Feature Does Not Work as Intended............................................... 17

Advisory —System Control: Clock Configuration Should Not be Changed When There are Pending or On-going

Accesses to Shared RAM (Cx and Sx) or to Analog Subsystem........................................................ 17

Advisory —ePWM: ePWM7 is Clocked by CPUCLK and Will Stop During IDLE.............................................. 17

Advisory —HWBIST: C28x HWBIST Should Not be Used ....................................................................... 18

Advisory —Crystal: Maximum Equivalent Series Resistance (ESR) Values are Reduced................................... 18

Advisory —Cortex-M3 Flash: C28x Reset While C28x Holding Pump Ownership Can Cause Erroneous Cortex-M3

Flash Reads .................................................................................................................... 19

Advisory —SSI: SSI Microwire Frame Format is Not Supported on This Device.............................................. 19

Advisory —USB/GPIO38: GPIO38/VBUS Cannot be Used as an Output ..................................................... 20

Advisory —USB: VBUS Pin May Clamp to 3.3-V Supply, Preventing Proper OTG Mode Operation....................... 20

Advisory —USB: Host Mode — Cannot Communicate With Low-Speed Device Through a Hub........................... 20

Advisory —RAM Controller: Cortex-M3 Correctable Error Address Register Always has Value 0x0 ....................... 21

Advisory —RAM Controller: C28x Correctable Error Address Register Always has Value 0x0 ............................ 21

Advisory —RAM Controller: Cortex-M3 Accesses to Shared RAM (Cx and Sx) and to MSG RAM Do Not Work When

Any Other Master (µDMA/C28x/DMA) Simultaneously Accesses the Same Memory................................ 21

Advisory —RAM Controller: µDMA Accesses to Shared RAM (Cx and Sx) and to MSG RAM Do Not Work When

Any Other Master (Cortex-M3/C28x/DMA) Simultaneously Accesses the Same Memory........................... 21

Advisory —eQEP: eQEP Inputs in GPIO Asynchronous Mode .................................................................. 22

Advisory —eQEP: Missed First Index Event........................................................................................ 22

Advisory —GPIO: GPIO38 and GPIO46 Shunt to V

Due to Fast Transient Sensitivity at High Temperature ........... 23

Advisory —GPIO: Pins GPIO38 and GPIO46 Cannot be Used for Functions Other Than USB ............................ 24

Advisory —GPIO: GPIOs on Port C Do Not Toggle Correctly When Using the GPCTOGGLE Register................... 24

Advisory —GPIO: Cortex-M3/C28x Reads GPIO State as ‘0’ When the GPIO is Mapped to the Other Core............. 24

Advisory —FPU: FPU Register Read Following MPYF32, ADDF32, SUBF32, or MACF32 ................................. 25

Advisory —FPU: FPU Register Write Followed by F32TOUI32, FRACF32, UI16TOF32, or F32TOUI32.................. 26

Advisory —FPU32 and VCU Back-to-Back Memory Accesses .................................................................. 27

Advisory —Control Subsystem I

C: FIFO Interrupt Trigger Levels Capped at 7............................................... 28

Advisory —Control Subsystem: Reset Value (/8) of CCLKCTL.CLKDIV Bit Field Violates the MIN Requirement

Mandated by the Data Manual for ACIBCLK, When the Input Clock to the Divider is Less Than 40 MHz ........ 28

Advisory —Debug: Cross-Trigger Functionality is Limited When Using Breakpoints on the C28x Core ................... 29

Advisory —Debug: Global Run of Cortex-M3 and TMS320C28x is not Operational.......................................... 29

Advisory —Debug: Control Subsystem Boot ROM M0 RAM-INIT Does Not Wait for RAM-INIT to Complete ............ 29

Advisory —NMI: Writing a "0" to Any of the CNMIFRC or MNMIFRC Register Bits Clears the Corresponding Flag Bit

in CNMIFLG or MNMIFLG.................................................................................................... 30

Advisory —PLL: Setting SYSPLLMULT or UPLLMULT to 0x0000 causes "/0" Condition in PLL Logic.................... 30

Advisory —Master Subsystem: MNMIFLG.NMIINT Bit Will Not be Set in Some Cases When an NMI is Still Pending.. 31

Advisory —Master Subsystem I

C: Data Hold Time Violates Philips

C Specification ...................................... 31

Advisory —Master Subsystem MPU: Memory Protection Unit is Disabled ..................................................... 31

Advisory —Master Subsystem Boot ROM: NMI Handler Can Return Before Clearing All the Pending NMIs, if There

SPRZ357J–August 2011–Revised July 2014 F28M35x Concerto™ MCU Silicon Errata

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