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Usage Notes and Known Design Exceptions to Functional Specifications

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Advisory Read of Clock Control Registers on C28x Memory Map is EALLOW-Protected

Revision(s) Affected 0

Details Clock Control Registers on the C28x memory map are read-protected by EALLOW.

Workaround(s) Enable EALLOW before reading the Clock Control Registers on the C28x memory map.

This is fixed in Revision A silicon.

Advisory CPU Self Test (HWBIST) is not Supported on Revision 0 Devices

Revision(s) Affected 0

Details HWBIST is not supported on revision 0 devices.

Workaround(s) None. This is fixed in Revision A silicon.

Advisory EPI: C28x Access to the EPI Bus on the Device

Revision(s) Affected 0

Details On Revision 0 silicon, the Control Subsystem (C28x core) cannot access the EPI. Only

the Master Subsystem (M3 core) can. Starting with Revision A silicon, the C28x has read

and write data access to the EPI peripheral. Note that C28x use of the EPI for program

execution is not supported in any silicon revision.

Workaround(s) This is fixed in Revision A silicon.

Advisory PBIST: DCAN0 Memory Cannot be Tested in Stand-alone Configuration

Revision(s) Affected 0

Details If DCAN0 memory is run in stand-alone mode using the PBIST logic, it will generate a

false fail regardless of memory integrity.

Workaround(s) DCAN0 memory must be tested in distributed compare mode only. This is fixed in

Revision A silicon.

F28M35x Concerto™ MCU Silicon Errata SPRZ357J–August 2011–Revised July 2014

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MAP electronics Cocerto-B Spezifikationen Seite 36