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Usage Notes and Known Design Exceptions to Functional Specifications
Advisory ADC: Initial Conversion
Revision(s) Affected 0, A, B
Details When the ADC conversions are initiated by any source of trigger in either sequential or
simultaneous sampling mode, the first sample may not be the correct conversion result.
Workaround(s) For sequential mode, discard the first sample at the beginning of every series of
conversions. For instance, if the application calls for a given series of conversions,
SOC0→SOC1→SOC2, to initiate periodically, then set up the series instead as
SOC0→SOC1→SOC2→SOC3 and only use the last three conversions, ADCRESULT1,
ADCRESULT2, ADCRESULT3, thereby discarding ADCRESULT0.
For simultaneous sample mode, discard the first sample of both the A and B channels at
the beginning of every series of conversions.
User application should validate if this workaround is acceptable in their application.
This issue is fixed completely by writing a 1 to the ADCNONOVERLAP bit in the
ADCTRL2 register, which only allows the sampling of ADC channels when the ADC is
finished with any pending conversion.
Advisory ADC: ADC Result Conversion When Sampling Ends on 14th Cycle of Previous
Conversion, ACQPS = 6 or 7
Revision(s) Affected 0, A, B
Details Each on-chip ADC takes 13 ADC clock cycles to complete a conversion after the
sampling phase has ended. The result is then presented to the bus controller on the 14th
cycle post-sampling and latched on the 15th cycle into the ADC result registers. If the
next conversion's sampling phase terminates on this 14th cycle, the results latched by
the bus controller into the result register are not assured to be valid across all operating
conditions.
Workaround(s) Some workarounds are as follows:
• Due to the nature of the sampling and conversion phases of the ADC, there are only
two values of ACQPS (which controls the sampling window) that would result in the
above condition occurring—ACQPS = 6 or 7. One solution is to avoid using these
values in ACQPS.
• When the ADCNONOVERLAP feature (bit 1 in ADCTRL2 register) is used, the above
condition will never be met; so the user is free to use any value of ACQPS desired.
• Depending on the frequency of ADC sampling used in the system, the user can
determine if their system will hit the above condition if the system requires the use of
ACQPS = 6 or 7. For instance, if the converter is continuously converting with
ACQPS = 6, the above condition will never be met because the end of the sampling
phase will always fall on the 13th cycle of the current conversion in progress.
15
SPRZ357J–August 2011–Revised July 2014 F28M35x Concerto™ MCU Silicon Errata
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Copyright © 2011–2014, Texas Instruments Incorporated
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