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Usage Notes and Known Design Exceptions to Functional Specifications

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Advisory Control Subsystem I

C: FIFO Interrupt Trigger Levels Capped at 7

Revision(s) Affected 0, A, B

Details The TXFFIL (Transmit FIFO Interrupt Level) bits in the I2C Transmit FIFO (I2CFFTX)

(I2CFFRX) register are capped to a maximum value of 7. Writes of values greater than 7

to these fields will be truncated to the lower 3 bits.

Workaround(s) Applications can poll the TXFFST (Transmit FIFO Status) and RXFFST (Receive FIFO

Status) bits in the I2CFFTX and I2CFFRX registers, respectively, for an accurate count

of the number of items in the FIFOs. Applications wishing to use I

C FIFO interrupts

must set the interrupt levels to 7 or less.

Advisory Control Subsystem: Reset Value (/8) of CCLKCTL.CLKDIV Bit Field Violates the

MIN Requirement Mandated by the Data Manual for ACIBCLK, When the Input

Clock to the Divider is Less Than 40 MHz

Revision(s) Affected 0

Details On power up or after an external reset (XRS), PLL is bypassed and the Master Boot

ROM configures the default SYSCLK divider to "/1". This makes the input clock to the

divider the same as OSCCLK. If OSCCLK is less than 40 MHz, then upon power up or

an external reset, ACIBCLK would be less than 5 MHz. However, this is not an issue

because the Analog Subsystem needs not be functional during boot time.

Workaround(s) An OTP function is provided in the Control Subsystem for users to call during their

application initialization process and before using Analog Subsystem peripherals on the

device. This function will configure the CCLKCTL divider as needed by the application.

This is fixed in Revision A silicon.

F28M35x Concerto™ MCU Silicon Errata SPRZ357J–August 2011–Revised July 2014

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MAP electronics Cocerto-B Spezifikationen Seite 28