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Usage Notes and Known Design Exceptions to Functional Specifications

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4 Usage Notes and Known Design Exceptions to Functional Specifications

NOTE: For errata relating to the Cortex-M3 r2p0 core, see the ARM Core Cortex-M3 / Cortex-M3

with ETM (AT420/AT425) Errata Notice at the ARM Ltd. website.

4.1 Usage Notes

Usage notes highlight and describe particular situations where the device's behavior may not match

presumed or documented behavior. This may include behaviors that affect device performance or

functional correctness. These usage notes will be incorporated into future documentation updates for the

device (such as the device-specific data sheet), and the behaviors they describe will not be altered in

future silicon revisions.

Table 2 shows which silicon revision(s) are affected by each usage note.

Table 2. List of Usage Notes

SILICON REVISION(S)

AFFECTED

TITLE

0 A B

PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Yes Yes Yes

Mask Clear

EPI: New Feature Addition to EPI Module Yes Yes

EPI: ALE Signal Polarity Yes Yes

EPI: CS0/CS1 Swap Yes Yes

Major Device Revision Yes

4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt

Mask Clear Usage Note

Revision(s) Affected: 0, A, B

Certain code sequences used for nested interrupts allow the CPU and PIE to enter an inconsistent state

that can trigger an unwanted interrupt. The conditions required to enter this state are:

1. A PIEACK clear is followed immediately by a global interrupt enable (EINT or asm(" CLRC INTM")).

2. A nested interrupt clears one or more PIEIER bits for its group.

Whether the unwanted interrupt is triggered depends on the configuration and timing of the other

interrupts in the system. This is expected to be a rare or nonexistent event in most applications. If it

happens, the unwanted interrupt will be the first one in the nested interrupt's PIE group, and will be

triggered after the nested interrupt re-enables CPU interrupts (EINT or asm(" CLRC INTM")).

Workaround: Add a NOP between the PIEACK write and the CPU interrupt enable. Example code is

shown below.

//Bad interrupt nesting code

PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE

EINT; //Enable nesting in the CPU

//Good interrupt nesting code

PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE

asm(" NOP"); //Wait for PIEACK to exit the pipeline

EINT; //Enable nesting in the CPU

F28M35x Concerto™ MCU Silicon Errata SPRZ357J–August 2011–Revised July 2014

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