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Usage Notes and Known Design Exceptions to Functional Specifications

Table 5 shows which silicon revision(s) are affected by each advisory.

Table 5. List of Advisories

SILICON REVISION(S)

AFFECTED

TITLE

0 A B

Analog Subsystem: Analog Subsystem Function InitAnalogSystemClock() is Incomplete Yes Yes Yes

Analog Subsystem: Potential Race Condition after Executing Analog Subsystem Functions Yes Yes Yes

AnalogClockEnable() or AnalogClockDisable()

ADC: Initial Conversion Yes Yes Yes

ADC: ADC Result Conversion When Sampling Ends on 14th Cycle of Previous Conversion, Yes Yes Yes

ACQPS = 6 or 7

ADC: Offset Self-Recalibration Requirement Yes Yes Yes

UART: RTRIS Bit in the UARTRIS Register is Only Set When the Interrupt is Enabled Yes Yes Yes

VREG: VREG 'Warn Lo/High' Feature Does Not Work as Intended Yes Yes Yes

System Control: Clock Configuration Should Not be Changed When There are Pending or On- Yes Yes Yes

going Accesses to Shared RAM (Cx and Sx) or to Analog Subsystem

ePWM: ePWM7 is Clocked by CPUCLK and Will Stop During IDLE Yes Yes Yes

HWBIST: C28x HWBIST Should Not be Used Yes Yes Yes

Crystal: Maximum Equivalent Series Resistance (ESR) Values are Reduced Yes Yes Yes

Cortex-M3 Flash: C28x Reset While C28x Holding Pump Ownership Can Cause Erroneous Yes Yes Yes

Cortex-M3 Flash Reads

SSI: SSI Microwire Frame Format is Not Supported on This Device Yes Yes Yes

USB/GPIO38: GPIO38/VBUS Cannot be Used as an Output Yes

USB: VBUS Pin May Clamp to 3.3-V Supply, Preventing Proper OTG Mode Operation Yes

USB: Host Mode — Cannot Communicate With Low-Speed Device Through a Hub Yes

RAM Controller: Cortex-M3 Correctable Error Address Register Always has Value 0x0 Yes Yes Yes

RAM Controller: C28x Correctable Error Address Register Always has Value 0x0 Yes

RAM Controller: Cortex-M3 Accesses to Shared RAM (Cx and Sx) and to MSG RAM Do Not Yes

Work When Any Other Master (μDMA/C28x/DMA) Simultaneously Accesses the Same Memory

RAM Controller: μDMA Accesses to Shared RAM (Cx and Sx) and to MSG RAM Do Not Work Yes

When Any Other Master (Cortex-M3/C28x/DMA) Simultaneously Accesses the Same Memory

eQEP: eQEP Inputs in GPIO Asynchronous Mode Yes Yes Yes

eQEP: Missed First Index Event Yes

GPIO: GPIO38 and GPIO46 Shunt to V

Due to Fast Transient Sensitivity at High Yes Yes Yes

Temperature

GPIO: Pins GPIO38 and GPIO46 Cannot be Used for Functions Other Than USB Yes

GPIO: GPIOs on Port C Do Not Toggle Correctly When Using the GPCTOGGLE Register Yes

GPIO: Cortex-M3/C28x Reads GPIO State as ‘0’ When the GPIO is Mapped to the Other Core Yes

FPU: FPU Register Read Following MPYF32, ADDF32, SUBF32, or MACF32 Yes Yes Yes

FPU: FPU Register Write Followed by F32TOUI32, FRACF32, UI16TOF32, or F32TOUI32 Yes

FPU32 and VCU Back-to-Back Memory Accesses Yes

Control Subsystem I

C: FIFO Interrupt Trigger Levels Capped at 7 Yes Yes Yes

Control Subsystem: Reset Value (/8) of CCLKCTL.CLKDIV Bit Field Violates the MIN Yes

Requirement Mandated by the Data Manual for ACIBCLK, When the Input Clock to the Divider

is Less Than 40 MHz

Debug: Cross-Trigger Functionality is Limited When Using Breakpoints on the C28x Core Yes

Debug: Global Run of Cortex-M3 and TMS320C28x is not Operational Yes

Debug: Control Subsystem Boot ROM M0 RAM-INIT Does Not Wait for RAM-INIT to Complete Yes

NMI: Writing a "0" to Any of the CNMIFRC or MNMIFRC Register Bits Clears the Yes

Corresponding Flag Bit in CNMIFLG or MNMIFLG

PLL: Setting SYSPLLMULT or UPLLMULT to 0x0000 causes "/0" Condition in PLL Logic Yes

Master Subsystem: MNMIFLG.NMIINT Bit Will Not be Set in Some Cases When an NMI is Still Yes

Pending

SPRZ357J–August 2011–Revised July 2014 F28M35x Concerto™ MCU Silicon Errata

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