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Known Design Marginality/Exceptions to Functional Specifications

4 Known Design Marginality/Exceptions to Functional Specifications

Table 2. Advisory List

Title ...................................................................................................................................... Page

Advisory —Debug: Global Run of Cortex™-M3 and TMS320C28x™ is not Operational ..................................... 8

Advisory —Debug: Cross-Trigger Functionality is Limited When Using Breakpoints on the C28x Core.................... 8

Advisory —Debug: Control Subsystem Boot ROM M0 RAM-INIT Does Not Wait for RAM-INIT to Complete ............. 8

Advisory —NMI: Writing a "0" to Any of the CNMIFRC/MNMIFRC Register Bits Clears the Corresponding Flag Bit in

CNMIFLG/MNMIFLG........................................................................................................... 9

Advisory —PLL: Setting SYSPLLMULT or UPLLMULT to 0x0000 causes "/0" Condition in PLL Logic .................... 9

Advisory —USB: VBUS Pin May Clamp to 3.3-V Supply, Preventing Proper OTG Mode Operation ....................... 9

Advisory —USB: Host Mode — Cannot Communicate With Low-Speed Device Through a Hub ........................... 9

Advisory —Control Subsystem: Reset Value (/8) of CCLKCTL.CLKDIV Bit Field Violates the MIN Requirement

Mandated by the Data Manual for ACIBCLK, When the Input Clock to the Divider is Less Than 40 MHz ....... 10

Advisory —Master Subsystem: MNMIFLG.NMIINT Bit Will Not be Set in Some Cases When an NMI is Still

Pending......................................................................................................................... 11

Advisory —Master Subsystem I2C: Data Hold Time Violates Philips

I2C Specification.................................... 11

Advisory —Master Subsystem MPU: Memory Protection Unit is Disabled .................................................... 11

Advisory —Master Subsystem Boot ROM: NMI Handler Can Return Before Clearing All the Pending NMIs, if There

is a Nested NMI ............................................................................................................... 12

Advisory —Master Boot ROM: NMI Handler Not Executed if NMI Occurs at Power Up or Immediately After a Reset . 12

Advisory —Master Boot ROM: Parallel Boot Mode Will Not Work as Intended............................................... 12

Advisory —GPIO: GPIOs on Port C Do Not Toggle Correctly When Using the GPCTOGGLE Register.................. 13

Advisory —C28x Flash: Code Executing From the C28x Subsystem Flash May be Subject to Unnecessary 1-Cycle

Delays .......................................................................................................................... 13

Advisory —C28x Clocking: EALLOW Protection of C28x Clocking Registers Prevents Read of Registers............... 13

Advisory —µDMA: No Transfer Completion Interrupt From SW Channels, Other Than Channel 30 ...................... 13

Advisory —Read of Clock Control Registers on C28x Memory Map is EALLOW-Protected................................ 14

Advisory —VCU: First CRC Calculation May Not be Correct.................................................................... 14

Advisory —UART: RTRIS Bit in the UARTRIS Register is Only Set When the Interrupt is Enabled....................... 14

Advisory —Flash ECC: When Program/Data Cache is Enabled, ECC Errors are Captured Only on a Single 64-Bit

Slice and Not on the Full 128-Bit Flash Bank Data Width .............................................................. 15

Advisory —Flash ECC: C28x 'Flash Uncorrectable' Error Generated When Executing F021 Flash API Functions

With Flash ECC Enabled..................................................................................................... 15

Advisory —VREG: VREG 'Warn Lo/High' Feature Does Not Work as Intended.............................................. 16

Advisory —Temperature Sensor: getTempSlope() and getTempOffset() Functions are not Available on TMX Silicon . 16

Advisory —EMAC: Resetting EMAC Controller Using SRCR2 Register Does Not Automatically Reset the Ethernet

PHY Via MII_PHYRST Signal ............................................................................................... 16

Advisory —System Control: Clock Configuration Should Not be Changed When There are Pending/On-going

Accesses to Shared RAM (Cx and Sx) or to Analog Subsystem....................................................... 16

Advisory —RAM Controller: Cortex™-M3 Accesses to Shared RAM (Cx and Sx) and to MSG RAM Do Not Work

When Any Other Master (µDMA/C28x/DMA) Simultaneously Accesses the Same Memory ....................... 17

Advisory —RAM Controller: µDMA Accesses to Shared RAM (Cx and Sx) and to MSG RAM Do Not Work When

Any Other Master (Cortex™-M3/C28x/DMA) Simultaneously Accesses the Same Memory ....................... 17

NOTE: For errata relating to the Cortex™-M3 r2p0 core, see the ARM Core Cortex-M3 / Cortex-M3

with ETM (AT420/AT425) Errata Notice at the ARM® Ltd. website.

SPRZ357B– August 2011– Revised January 2012 F28M35x Concerto MCU Silicon Errata

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