x 980
YMLLLLS
YM
LLLL
S
$$
980
G4
Lot Trace Code
2-Digit Year/Month Code
Assembly Lot
Assembly Site Code
Wafer Fab Code as applicable
TI EIA Code
Green (Low Halogen and RoHS-compliant)
=
=
=
=
=
=
=
$$-YMLLLLS
G4
F28M35H52C1RFPT
Package
Pin 1
PREFIX
x
x
p
no prefix
=
=
=
experimental device
prototype device
qualified device
F28M3
DEVICE FAMILY
F28M3 = Concerto
TM
C
B
=
=
Connectivity
Base
PERIPHERALS
C
2 = 256KB each core
3 = additional 256KB to one core
5 = 512KB each core
(A)
FLASH
5
0
2
=
=
72KB
additional 64KB of masterable RAM
RAM
2
H
M
E
=
=
=
150 / 75 MHz or 100 / 100 MHz
75 / 75 MHz
60 / 60 MHz
PERFORMANCE
(C28x Speed / Cortex -M3 Speed)
TM TM
H
5
SERIES NUMBER
1 = 144 pins
1
PINS
RFP
PACKAGE TYPE
144-Pin RFP PowerPAD
Thermally Enhanced Thin Quad Flatpack (HTQFP)
TM
TEMPERATURE RANGE
T
−40°C to 105°C
−40°C to 125°C
−40°C to 125°C
(Q refers to Q100 qualification
for automotive applications.)
T
S
Q
=
=
=
Device Markings
www.ti.com
3 Device Markings
Figure 1 provides an example of the Concerto device markings and defines each of the markings. The
device revision can be determined by the symbols marked on the top of the package as shown in
Figure 1. Some prototype devices may have markings different from those illustrated. Figure 2 shows an
example of the device nomenclature.
Figure 1. Example of Device Markings
Table 1. Determining Silicon Revision From Lot Trace Code
SECOND LETTER
IN PREFIX OF SILICON REVISION REVISION ID COMMENTS
LOT TRACE CODE
Blank Indicates Revision 0 Cortex™-M3: 0x400F EC00 This silicon revision is
(no second letter in prefix) C28x™: 0x0883 available as x (experimental
device).
0x0000
A The additional 256KB is added to the Cortex™-M3 core (Connectivity Devices) or to the C28x™ core (Base Devices).
Figure 2. Example of Device Nomenclature
6
F28M35x Concerto MCU Silicon Errata SPRZ357B–August 2011–Revised January 2012
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Copyright © 2011–2012, Texas Instruments Incorporated
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