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Known Design Marginality/Exceptions to Functional Specifications

Advisory Master Subsystem: MNMIFLG.NMIINT Bit Will Not be Set in Some Cases When an

NMI is Still Pending

Revision(s) Affected 0

Details On the Master Subsystem, if there is a nested NMI and if the user clears the

MNMIFLG.NMIINT bit before clearing all the other pending flags while returning from the

first NMI handler, then the MNMIFLG.NMIINT bit will not be set while the second NMI is

still pending. This pending NMI will keep the MNMIWD counter running and will reset the

device if the pending flag is not cleared on time.

If the second NMI among the nested NMI is a Missing-clock NMI, then immediately after

MNMIWD reset, there will be another NMI because of the MCLKSTS bit being set.

Workaround(s) User NMI handler should not depend on the MNMIFLG.NMIINT bit to determine if there

is an active NMI pending and should instead look at all the individual bits to check if an

NMI is pending.

This will be fixed in the next revision of the silicon.

Advisory Master Subsystem I2C: Data Hold Time Violates Philips

I2C Specification

Revision(s) Affected 0

Details The Master subsystem I2C module’s data hold time on F28M35x Concerto devices is a

minimum of 2 system clock cycles, which violates the Philips® I2C specification

requirement of a minimum of 0 system clock cycle.

Workaround(s) None

Advisory Master Subsystem MPU: Memory Protection Unit is Disabled

Revision(s) Affected 0

Details The Cortex™-M3 Memory Protection Unit (MPU) is disabled on the F28M35x Revision 0

silicon.

Workaround(s) None. This will be fixed on the next revision of the silicon.

SPRZ357B– August 2011– Revised January 2012 F28M35x Concerto MCU Silicon Errata

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MAP electronics Cocerto-B Spezifikationen Seite 11